This invention relates to a method of manufacturing stacked-gate nonvolatile semiconductor memory devices applied to flash memory or the like.
Generally, in a nonvolatile semiconductor memory device composed of an EEPROM, stacked-gate memory cells are formed using a first resist pattern as a mask. Thereafter, the first resist pattern is removed and then a second resist pattern is formed to produce a gate electrode for a peripheral circuit. Next, with the gate electrode of a memory cell array section as a mask, a field oxide film is etched away in such a manner that it is self-aligned to one end of the gate electrode to form a source interconnection region.
FIGS. 12A to 18C show a method of manufacturing conventional nonvolatile semiconductor memory devices, such as NOR flash memory. FIGS. 12A, 13A, 14A, 15A, 16A, 17A, and 18A each illustrate a memory cell section. FIGS. 12B, 13B, 14B, 15B, 16B, 17B, and 18B each represent a transistor constituting a peripheral circuit section. FIGS. 15C, 16C, 17C, and 18C each depict the structure of a field oxide film section.
First, as shown in FIG. 12A, a gate insulating film 12, a polysilicon film 13 making a floating gate, an ONO (oxide nitride oxide) insulating film 14, a polysilicon film 15 making a control gate, and a tungsten silicide film (WSi) 16 are stacked in that order on a semiconductor substrate 11 in a memory cell section. On the tungsten silicide film 16, a first resist 17 is formed, which is subjected to pattering.
Next, using the pattern of the first resist 17 as a mask, the tungsten silicide film 16, polysilicon film 15, ONO insulating film 14, and polysilicon film 13 are etched in that order to form a gate electrode 18 for the memory cell as shown in FIG. 13A.
At this time, the peripheral circuit section is constructed as shown in FIGS. 12B and 13B. Specifically, an insulating film 19, the polysilicon film 15 making a gate electrode, and the tungsten silicide film 16 are stacked in that order on the semiconductor substrate 11. The tungsten silicide film 16 is covered with the first resist 17.
After the first resist 17 has been peeled, a second resist 20 is formed all over the surface as shown in FIGS. 14A and 14B. Using the resist pattern as a mask, the tungsten silicide film 16 and polysilicon film 15 in the peripheral circuit section are etched in that order to form a gate electrode.
Then, removing the second resist 20 forms the gate electrode 21 of a transistor constituting the peripheral circuit section as shown in FIG. 15B. FIG. 15C shows word lines WL formed on the field oxide film 23. The word lines WL are formed integrally with the control gates constituting the memory cells.
Then, as shown in FIGS. 16A, 16B, and 16C, a third resist 22 is formed all over the surface. The third resist 22 is subjected to patterning so as to cover every other space between the gate electrodes 18 and every other space between the word lines WL and expose every other space between the gate electrodes 18 and every other space between the word lines WL.
Next, as shown in FIGS. 17A, 17B, and 17C, with the third resist 22 and the tungsten silicide film 16 of the gate electrode 18 as a mask, the gate insulating film 12 is etched in such a manner that the gate insulating film is self-aligned to the gate electrode 18. This forms a common source region 24. At the same time, using the word lines WL as a mask, the field oxide film 23 is etched to form the common source region 24.
Thereafter, the third resist 22 is removed and then a fourth resist 26 is formed as shown in FIGS. 18A, 18B, and 18C. With the fourth resist 26 as a mask, ions of n-type impurities, for example, arsenic (As), are implanted into the semiconductor substrate 11 to form a common source line 25.
The conventional manufacturing method requires two lithographic processes: the lithographic process of forming the gate electrode of the memory cell section and that of forming the gate electrode of the peripheral circuit section. In these lithographic processes, the dimensions are difficult to control. Furthermore, as the memory cells are made much finer, the space between adjacent gate electrodes gets much narrower. As a result, it is more difficult to etch the space between the gate electrodes with a resist mask.
During ion implantation to form the common source line, part of the gate electrode 18 constituting the memory cell section and part of the word lines are exposed at the fourth resist 26. This permits arsenic to enter the tungsten silicide film constituting the gate electrodes and word lines, which causes the problem of lessening the margin for abnormal oxidation of the tungsten silicide film in a subsequent oxidation process.